Date of Award
8-2018
Degree Type
Dissertation
Degree Name
Doctor of Philosophy (PhD)
Department
Electrical and Computer Engineering
Committee Chair
Peide Ye
Committee Member 1
Mark S. Lundstrom
Committee Member 2
Joerg Appenzeller
Committee Member 3
Zhihong Chen
Abstract
With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel device structures have been extensively studied and attracted a lot of attention in solid-state device research. In this dissertation, solid-state electron devices for post-Si CMOS applications are explored including both new materials such as III-V and 2D materials and new device structures such as tunneling field-effect transistors and negative capacitance field-effect transistors. Multiple critical challenges in applying such new materials and new device structures are addressed and the key achievements in this dissertation are summarized as follows: 1) Development of fabrication process technology for ultra-scaled planar and 3D InGaAs MOSFETs. 2) Interface passivation by forming gas anneal on InGaAs gate-all-around MOSFETs. 3) Characterization methods for ultra-scaled MOSFETs, including a correction to subthreshold method and low frequency noise characterization in short channel devices. 4) Development of short channel InGaAs planar and 3D gate-allaround tunneling field-effect transistors. 5) Negative capacitance field-effect transistors with hysteresis-free and bi-directional sub-thermionic subthreshold slope and the integration with various channel materials such as InGaAs and MoS2.
Recommended Citation
Si, Mengwei, "III-V and 2D Devices: from MOSFETs to Steep-Slope Transistors" (2018). Open Access Dissertations. 2072.
https://docs.lib.purdue.edu/open_access_dissertations/2072