Date of Award

12-2017

Degree Type

Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Electrical and Computer Engineering

Committee Chair

Saeed Mohammadi

Committee Member 1

Kaushik Roy

Committee Member 2

Byunghoo Jung

Committee Member 3

Eugenio Culurciello

Abstract

Preserving battery life in duty-cycled sensor nodes requires minimizing energy use in the active region. Lowering the power supply of CMOS gates down into sub-threshold mode is a good way to decrease energy. In this work, a unique technique to control the current in CMOS gates to reliably operate them in sub-threshold mode is described. Compared to the current state-of-theart for running digital gates in the sub-threshold regime, this work is often superior in its lack of complexity and in reduced variance in delay caused by process variations. In addition to presenting the design considerations, a demonstration of a complete digital design flow is given using the custom gates. An AES128 encryption/decryption engine is designed using the aforementioned digital flow in a commercial 180nm process. The resulting design has a ratio of maximum to minimum frequency variation over corners of only 50% with a 0.3V power supply where the same ratio with standard CMOS gates biased under the same supply voltage is 5600%. In addition, the custom gates are used to design a Wallace tree multiplier in an SOI 45nm process that is fully functional with an optimum energy power supply level of 0.34V with a typical operating frequency of 8 MHz having a variation over corners of 80%.

For a proof of concept memory chip designed in this work, the architecture uses a logiccompatible CMOS process particularly suitable for embedded applications. The differential pair construct causes the read and refresh power to be independent of any process parameter including the within-die threshold voltage. The current stop feature keeps the read voltage transition low to further minimize read power. The bit cell operates in both single bit BASE2 and multi-bit BASE4 modes. An expression for the read signal was verified with bit cell simulations. These simulations also compare the performance impact of threshold voltage variance in the architecture with a standard gain cell. A DRAM bit cell array was fabricated in the XFab 180nm CMOS process. Measured waveforms closely match theoretical results obtained from a system simulation. The silicon retention time was measured at room temperature and is greater than 150 ms in BASE2 mode and greater than 75 ms in BASE4 mode. 180nm, 25C analysis predicts 0.8uW/Mbit refresh power at 630 MHz, the lowest in the literature. Further: the memory bit cell architecture presented here has a refresh power delay product several times lower than any other published architecture.

The current controlled memory architecture in this work improves or overcomes the drawbacks of the 1T1C and gain cell memory architectures. A current controlled memory design was fabricated as a 131K bit array in an 180nm process to provide silicon proof. The bit cell configuration with shared read and write bit cells gives effectively two memory banks. The grouping of rows together into common source domains allows only two opamps to control the current in all the bit cells across the whole chip. The sense amplifiers have a globally controlled switching threshold point and keep their static power in the nano-amp range. The bit cells can operate either in BASE2 or BASE4 mode and the read bit line transitions are reduced with a current stop construct. Parts were received from the foundry in an 84-pin PLCC and were tested at a number of locations on the die. They proved to be fully functional in BASE4. The silicon retention time was measured at room temperature and was greater than four seconds.

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