Date of Award

12-2017

Degree Type

Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Electrical and Computer Engineering

Committee Chair

Irith Pomeranz

Committee Member 1

Anand Raghunathan

Committee Member 2

Vijay Raghunathan

Committee Member 3

Enamul Amyeen

Abstract

A tester collects failure information for faulty circuits in order to perform defect diagnosis and derive information about the defects that is important for yield improvement. The increase in the complexity of the semiconductor manufacturing process and the higher number of defects due to scaling have caused an increase in the volume of fail data generated. However, with limited tester memory, fail data collection may terminate without acquiring data that is important for diagnosis. Additionally, a large amount of tester time is spent in data collection, increasing the overall test cost. This thesis presents several algorithms for efficient fail data collection for defect diagnosis in order to resolve these issues. They include algorithms that run on the tester during fail data collection, and pre-processing algorithms that reorder tests prior to data collection. The goal of these algorithms is to ensure that data, which is important for defect diagnosis, is available when fail data collection stops. They also aim to terminate fail data collection early to save tester time. A faulty circuit may contain either logic defects, scan defects, or both. The first part of this work considers circuits with logic defects. An algorithm called the dynamic N-cover algorithm is proposed that analyzes failing tests during data collection, to determine if they are important for diagnosis. Tests are added to or eliminated from the fail data-logs based on this analysis. When sufficient information is collected for accurate defect diagnosis, fail data collection is terminated, reducing the overall tester time. In order to further support early termination of fail data collection, a test

reordering algorithm is proposed that orders tests based on diagnostic information extracted from faulty circuits. The second part of this thesis focuses on circuits with scan defects. The nature of scan defects is such that only the first few failing tests are logged by the tester, adversely impacting the quality of scan diagnosis results. A scan fail data collection algorithm is discussed that runs on the tester to determine the fail data to be collected for a faulty unit. It analyzes failing tests beyond the tester memory limit and stores data only for the tests that are judged as useful. A termination condition is used to limit the tester time spent in data collection. Lastly, a test reordering algorithm is proposed to reorder tests before fail data collection begins to improve the quality of scan diagnosis results when a limited amount of data is collected by the tester.

Download

Share

COinS