Abstract
The one-dimensional, cylindrical nature of single-walled carbon nanotubes (SWCNTs) suggests that the ideal gating geometry for nanotube field-effect transistors (FETs) is a surround gate (SG). Using vertical SWCNTs templated in porous anodic alumina, SGs are formed using top-down processes for the dielectric/metal depositions and definition of the channel length. Surround gates allow aggressive scaling of the channel to 25% of the length attainable with a bottom-gate geometry without incurring short-channel effects. The process demonstrated here for forming SGs on vertical SWCNTs is amenable for large-scale fabrication of multinanotube FETs.
Keywords
field-effect transistor, high-performance electronics, porous alumina, arrays, lithography, fabrication, templates, circuits, contact, silicon
Date of this Version
3-2009
Comments
©2009 American Vacuum Society. doi:10.1116/1.3054266