Date of Award
Doctor of Philosophy (PhD)
Electrical and Computer Engineering
Committee Member 1
Committee Member 2
Committee Member 3
Committee Member 4
The improvements in the density of integrated circuits and device performance have been achieved through a long journey of device downscaling and increase in chip size. The tremendous push of the industry to aggressively scale devices has increased parasitic effects generated by an increase in the resistivity of the wire metallization which negatively affects the chip performance. Therefore, a careful design of interconnects is essential to reduce these parasitic effects. This work presents the first study where a fully atomistic basis has been used to describe realistic copper interconnects as used in the industry to identify the effects on resistivity. Initially in this work, the orientation effects on the specific resistance of copper grain boundaries are studied systematically with two different atomistic tight-binding methods. A methodology is developed to model the specific resistance of grain boundaries at the ballistic limit using the non-equilibrium Green’s functions. The methodology is validated against first-principles calculations for thin films with a single coincident grain boundary and then a statistical ensemble of 600 large, random structures with grains is studied. Finally, a compact model for grain-boundary-specific resistance is constructed based on a neural network.
Based on the methodology developed for copper grain boundaries, other scattering effects such as surface roughness and electron-phonon were included for thin films as suggested by the ITRS roadmap. These results quantify the effect of each parameter individually and can guide the design of electronic devices that use less power and have better performance
Valencia, Daniel, "Modeling Electronic Transport in Metal Interconnects" (2018). Open Access Dissertations. 2090.