Abstract
Planar and 3-dimensional (3D) buried-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) have been experimentally demonstrated at deep-submicron gate lengths. The effect of (NH(4))(2)S passivation with different concentrations (20%, 10%, or 5%) on the off-state performance of these devices has been systematically studied. 10% (Na(4))(2)S treatment is found to yield the optimized high-k/InP harrier layer interface property, resulting in a minimum subthreshold swing (SS) lower than 100 mV/dec. Moreover, the 3D device structure greatly improves the off-state performance and facilitates enhancement-mode operation. A scaling metrics study has been carried out for 10% (NH(4))(2)S treated 3D devices with gate lengths down to 100 nm, With the optimized interface passivation, 3D III-V MOSFETs are very promising for future high-speed low-power logic applications. (C) 2011 American Institute of Physics [doi:10.1063/1.3651754]
Keywords
MOSFET; GATE; CHANNEL
DOI
10.1063/1.3651754
Citation
Applied Physics Letters: Volume 99, Issue 15
Date of this Version
10-10-2011
Recommended Citation
Gu, J J; Neal, A T.; and Ye, P D., "Effects of (NH(4))(2)S passivation on the off-state performance of 3-dimensional InGaAs metal-oxide-semiconductor field-effect transistors" (2011). Birck and NCN Publications. Paper 845.
http://dx.doi.org/10.1063/1.3651754
Comments
Copyright (2011) American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics. The following article appeared in Applied Physics Letters: Volume 99, Issue 15 and may be found at http://dx.doi.org/10.1063/1.3651754. The following article has been submitted to/accepted by Applied Physics Letters. Copyright (2011) J. J. Gu, A. T. Neal, and P. D. Ye. This article is distributed under a Creative Commons Attribution 3.0 Unported License.