Substrate Gating of Contact Resistance in Graphene Transistors

Dionisis Berdebes, Purdue University
Tony Low
Yang Sui
Joerg Appenzeller, Purdue University
Mark Lundstrom, Purdue University

Abstract

Metal contacts have been identified to be a key technological bottleneck for the realization of viable graphene electronics. Recently, it has been observed that for structures that possess both a top and a bottom gate, the electron-hole conductance asymmetry can be modulated by the bottom gate. In this paper, we explain this observation by postulating the presence of an effective thin interfacial dielectric layer between the metal contact and the underlying graphene. Electrical results from quantum transport calculations accounting for this modified electrostatics corroborate well with the experimentally measured contact resistances. This paper indicates that the engineering of a metal-graphene interface is a crucial step toward reducing the contact resistance for high-performance graphene transistors.

Discipline(s)

Nanoscience and Nanotechnology