Broken-Gap Tunnel MOSFET: A Constant-Slope Sub-60-mV/decade Transistor

Joshua Thomas Smith, Purdue University
Saptarshi Das, Purdue University
Joerg Appenzeller, Purdue University

Abstract

We propose a novel low-power transistor device, called the broken-gap tunnel MOSFET (BG-TMOS), which is capable of achieving constant sub-60-mV/decade inverse subthreshold slopes S at room temperature. Structurally, the device resembles an ungated broken-gap heterostructure Esaki region in series with a conventional MOSFET. The gate voltage independence of the energy spacing between the conduction and valence bands at the heterojunction is the key to producing a constant S < 60 mV/decade, which can be tuned by properly engineering the material composition at this interface. In contrast to the tunneling field-effect transistor, the tunnel junction in the BG-TMOS is independent of the electrostatics in the channel region, enabling the use of 2-D architectures for improved current drive without degradation of S—attractive features from a circuit design perspective. Simulations show that the BG-TMOS can exceed MOSFET performance at low supply voltages.

Discipline(s)

Electronic Devices and Semiconductor Manufacturing | Nanotechnology Fabrication