Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs

Author

• Giuseppe Carlo Tettamanzi, Delft University of Technology, The Netherlands
• Abhijeet Paul, NCN, Purdue University
• Sunhee Lee, NCN, Purdue University
• Saumitra R. Mehrotra, NCN, Purdue University
• Nadine Collaert, IMEC, Belgium
• Serge Biesemans, IMEC, Belgium
• Gerhard Klimeck, NCN, Purdue UniversityFollow
• Sven Rogge, Delft University of Technology, The Netherlands

Abstract

The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.

Comments

Giuseppe Carlo Tettamanzi, Abhijeet Paul, Sunhee Lee, Saumitra R. Mehrotra, Nadine Collaert, Serge Biesemans, Gerhard Klimeck, Sven Rogge. Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs. IEEE Electron Device Letters (Volume: 32, Issue: 4, April 2011) DOI: 10.1109/LED.2011.2106150

DOI

10.1109/LED.2011.2106150

Citation

Giuseppe Carlo Tettamanzi, Abhijeet Paul, Sunhee Lee, Saumitra R. Mehrotra, Nadine Collaert, Serge Biesemans, Gerhard Klimeck, Sven Rogge. Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs. IEEE Electron Device Letters (Volume: 32, Issue: 4, April 2011) DOI: 10.1109/LED.2011.2106150

Date of this Version

11-11-2010

Recommended Citation

Tettamanzi, Giuseppe Carlo; Paul, Abhijeet; Lee, Sunhee; Mehrotra, Saumitra R.; Collaert, Nadine; Biesemans, Serge; Klimeck, Gerhard; and Rogge, Sven, "Interface Trap Density Metrology of State-of-the-Art Undoped Si n-FinFETs" (2010). Birck and NCN Publications. Paper 732.
http://dx.doi.org/10.1109/LED.2011.2106150