Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing
Abstract
We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laster annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating S as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggresively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver S-values below 60 mV/dec for optimized device structures.
Keywords
Excimer laser annealing, nanowire tunneling field-effect transistor, steep-slope transistors, ultrathin-body silicon-on-insulator
DOI
10.1109/TED.2011.2135355
Citation
J. T. Smith, C. Sandow, S. Das, R. A. Minamisawa, S. Mantl, and J. Appenzeller, IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1822-1829, Jul. 2011
Date of this Version
6-21-2011
Recommended Citation
Smith, Joshua Thomas; Sandow, Christian; Das, Saptarshi; Minamisawa, Renato A.; Mantl, Siegfried; and Appenzeller, Joerg, "Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing" (2011). Birck and NCN Publications. Paper 711.
http://dx.doi.org/10.1109/TED.2011.2135355
Comments
Joshua T. Smith, Christian Sandow, Saptarshi Das, Renato A. Minamisawa, Siegfried Mantl, Joerg Appenzeller. Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing. IEEE Transactions on Electron Devices (Volume: 58, Issue: 7, July 2011)