Toward surround gates on vertical single-walled carbon nanotube devices

Author

• Aaron D. Franklin, Birck Nanotechnology Center and School of Electrical and Computer Engineering, Purdue UniversityFollow
• Robert A. Sayer, Birck Nanotechnology Center and School of Mechanical Engineering, Purdue UniversityFollow
• Timothy D. Sands, Birck Nanotechnology Center, School of Electrical and Computer Engineering and School of Materials Engineering, Purdue UniversityFollow
• Timothy Fisher, Birck Nanotechnology Center and School of Mechanical Engineering, Purdue UniversityFollow
• David B. Janes, Birck Nanotechnology Center and School of Electrical and Computer Engineering, Purdue UniversityFollow

Abstract

The one-dimensional, cylindrical nature of single-walled carbon nanotubes (SWCNTs) suggests that the ideal gating geometry for nanotube field-effect transistors (FETs) is a surround gate (SG). Using vertical SWCNTs templated in porous anodic alumina, SGs are formed using top-down processes for the dielectric/metal depositions and definition of the channel length. Surround gates allow aggressive scaling of the channel to 25% of the length attainable with a bottom-gate geometry without incurring short-channel effects. The process demonstrated here for forming SGs on vertical SWCNTs is amenable for large-scale fabrication of multinanotube FETs.

Keywords

FIELD-EFFECT TRANSISTOR; HIGH-PERFORMANCE ELECTRONICS; POROUS ALUMINA; ARRAYS; LITHOGRAPHY; FABRICATION; TEMPLATES; CIRCUITS; CONTACT; SILICON

Citation

DOI: 10.1116/1.3054266

Date of this Version

3-30-2009

Recommended Citation

Franklin, Aaron D.; Sayer, Robert A.; Sands, Timothy D.; Fisher, Timothy; and Janes, David B., "Toward surround gates on vertical single-walled carbon nanotube devices" (2009). Birck and NCN Publications. Paper 358.
https://docs.lib.purdue.edu/nanopub/358