A Self-Aligned Process for High-Voltage, Short-Channel Vertical DMOSFETs in 4H-SiC

Author

• Maherin Martin, School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University
• Asmita Saha, School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University
• James A. Cooper Jr., School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue UniversityFollow

Abstract

In this paper, we describe a self-aligned process to produce short-channel vertical power DMOSFETs in 4H-SiC. By reducing the channel length to 0 5 m, the specific on-resistance of the MOSFET channel is proportionally reduced, significantly enhancing performance.

Keywords

Counter-doping, DMOS, high-voltage MOSFET, nitric oxide (NO) anneal, self-aligned, short-channel, SiC

Date of this Version

10-8-2004

Recommended Citation

Martin, Maherin; Saha, Asmita; and Cooper, James A. Jr., "A Self-Aligned Process for High-Voltage, Short-Channel Vertical DMOSFETs in 4H-SiC" (2004). Birck and NCN Publications. Paper 253.
https://docs.lib.purdue.edu/nanopub/253