Limitations of the High-Low C-V Technique for MOS Interfaces With Large Time Constant Dispersion
Date of this Version
3-2013Citation
IEEE Transactions on Electron Devices ( Volume: 60, Issue: 3, March 2013 )
Abstract
We discuss the limitations of the high-low CV technique in evaluating the interface trap density (D-TT) in MOS samples with a large time constant dispersion, as occurs in silicon carbide (SiC). We show that the high-low technique can seriously underestimate D-IT for samples with large time constant dispersion, even if elevated temperatures are used to extend the range of validity.
Discipline(s)
Nanoscience and Nanotechnology
Comments
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