Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits
Abstract
In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL). To assess the performance of the proposed structure, some device characteristics of the structure have been compared with those of silicon on insulator-FinFET (SOI-FinFET) and Bulk-FinFET structures (where the BOX layer covers all the regions except the channel region). In addition, we compare different characteristics of static random access memory (SRAM) cells based on the proposed device structure as well as SOI-FinFET and Bulk-FinFET structures. The characteristics include standby power consumption, and read static noise margin (SNM). Finally, the behavior of the proposed device in the presence of dimensional variations (channel length and thin film thickness variations) and random dopant fluctuation (RDF) are studied and compared with those of the other two structures. (C) 2012 Elsevier B.V. All rights reserved.
Keywords
FinFET; DIBL; Ground plane; Process variation; RDF; SRAM cell; SOI MOSFET; BULK FINFET; DOUBLE-GATE; BODY; OPTIMIZATION; DEVICES; PERFORMANCE; DESIGN; FLUCTUATIONS; MODEL
DOI
10.1016/j.mee.2012.01.009
Citation
Microelectronic Engineering Volume 95, July 2012, Pages 74–82
Date of this Version
7-2012
Recommended Citation
Saremi, Mehdi; Afzali-Kusha, Ali; and Mohammadi, Saeed, "Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits" (2012). Birck and NCN Publications. Paper 1172.
http://dx.doi.org/10.1016/j.mee.2012.01.009