Templated Vertical Carbon Nanotube Transistors

Authors

Aaron D. Franklin, Birck Nanotechnology Center and School of Elecrical and Computer Engineering, Purdue UniversityFollow
Joshua T. Smith, Birck Nanotechnology Center and School of Electrical and Computer Engineering, Purdue UniversityFollow
Timothy D. Sands, Birck Nanotechnology Center, School of Electrical and Computer Engineering, and School of Materials Engineering, Purdue UniversityFollow
Timothy S. Fisher, Birck Nanotechnology Center and School of Mechanical Engineering, Purdue UniversityFollow
David B. Janes, Birck Nanotechnology Center and School of Electrical and Computer Engineering, Purdue UniversityFollow

Abstract

Single-walled carbon nanotubes (CNTs) are a potential channel material for the next generation field-effect transistors (FETs). With properties such as quasi-ballistic transport and high thermal conductivity, CNTFETs have the ability to outperform Si MOSFETs. To date, all reported CNTFETs have been created in a planar geometry, with the CNT horizontal to the supporting substrate. While planar CNTFETs have provided an important plaform for exploring device properties, they have yet to overcome the impending issues related to large-scale device fabrication. Obstracles such as precise placement, addressability, and high-density integration of CNTFETs can be overcome using a vertical device geometry. In the present work, vertical CNTs (v-CNTs) are synthesized within porous alumina templates and contacted in situ with vertical Pd nanowries. Semi-vertical CNTFETs are subjsequently fabricated to provide a comparison of the vertical nanowire contact to a more conventional planar content. Futher fabrication work is also presented, displyaing our progress towards fabricating addressable arrays of v-CNTFETs.

Keywords

Carbon nanotubes (CNTs), field-effect transistors (FETs)

Date of this Version

April 2007