Abstract
This paper analyzes some of the difficulties of emulating a Complex Instruction Set Computer (CISC) with a Reduced Instruction Set Computer (RISC). It will be shown that although the speed advantage of a RISC is sacrificed, a CISC can be emulated with the exception of software constructs that support nonstandard hardware interfaces. Some concrete examples will be used to help illustrate the execution- time bottlenecks as well as to discuss possible solutions from an architectural point of view for both Silicon and Gallium Arsenide (GaAs). In addition, it will be shown that the most efficient method of emulation involves debugging compiled High-Level Language (HLL) source code on a CISC, and then recompiling the HLL code with a compiler that is familiar with the target RISC architecture
Date of this Version
4-1-1988
Comments
This research (especially in its final phases) was partially supported by NCR Corporation, World’s Headquarters, Dayton, Ohio