Abstract
This paper presents several new array multiplier architectures for reducing the switching activity in general digital signal processing applications. A general cellular structure is described which can be used to obtain any array multiplier suitable for a given application. The switching activity at the output nodes of the cells in this structure is analyzed and compared with a tree multiplier based on 4 : 2 compressors. It is shown that the relative inlprovement in power is a function of statistical properties of the signal. It is also shown that selection of appropriate array architecture can give up to 40% reduction in switching activity compared to a tree multiplier, and more than 3 times less switching activity compared to the widely used least-szgnzficant-bzt-first array multiplier for commonly occurring situations. We also outline applications of the proposed multipliers to the areas of low power quantization, reconfigu~.able computing and high-level synthesis for low power.
Date of this Version
March 1999