A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS

Authors

Ik Joon Chang
Jae-Joon Kim
Sang Phill Park
Kaushik Roy

Abstract

We demonstrate a 10T subthreshold SRAM with an efficient bit-interleaving structure for soft-error tolerance and a differential read scheme for improved stability. The 32kb (256128) SRAM array is fabricated in 90nm CMOS and operates at 31.25kHz at 0.18V With more aggressive wordline boosting, the V DD can be reduced to 0.16V At the minimum VDD condition, the operating frequency is 500Hz and the power consumption is 0.123W.

Comments

Publisher retains content copyright.

Keywords

Optical design, Static random access storage

Date of this Version

January 2008

DOI

http://dx.doi.org/10.1109/ISSCC.2008.4523220

Published in:

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 51,(2008) 388-389+622+375-388-389+622+375;