A 135mV 0.13W process tolerant 6T subthreshold DTMOS SRAM in 90nm technology

Authors

Myeong-Enn Hwang
Kaushik Roy

Abstract

Cell stability and tolerance to process variation are of primary importance in subthreshold SRAMs. We propose a DTMOS based 6T SRAM suitable for subthreshold operation. For variation tolerant memory peripheral circuitry, we apply -ratio modulation technique. DTMOS SRAM array fabricated in 90nm technology operates down to 135mV consuming 0.13W at 750Hz. The proposed SRAM achieves 200% improvement in read static noise margin at iso-area compared to the conventional 6T SRAM at a supply voltage of 200mV.

Comments

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Keywords

integrated circuit layout, Integrated circuits, Modulation, nanotechnology, Static random access storage

Date of this Version

January 2008

DOI

http://dx.doi.org/10.1109/CICC.2008.4672109

Published in:

Proceedings of the Custom Integrated Circuits Conference (2008) 419-422;