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UVM, System on Chip


Nowadays, system-on-chips (SoC) are widely applied to perform any computing task. They are used in personal computers, embedded systems, and mobile computing. During the design of an SoC, testing and debugging play important roles to ensure the correct functionalities before sending the chip for fabrication. There are several different verification methods, among which the Universal Verification Methodology (UVM) is the one we are using. It is written in SystemVerilog and is an efficient method for verifying digital designs that is standardized in the industry. Following UVM, we can create scalable and well-formatted testbenches that can be reused for other components and projects. UVM also allows us to generate randomized test cases through software simulations. The purpose of this research project is to learn about the syntax and structure of UVM and to apply it to rigorously validate the functionalities of a register transfer level (RTL) block, and particularly a recently developed Serial Peripheral Interface (SPI) block. We have analyzed the original design and the codes for SPI in order to determine the key features that need to be tested. By examining the waveform of the design, we came up with a test plan which includes testcases and checkers. We have also thoroughly studied the structure of the UVM testbench and the usage for each component. For the next step, we will start implementing the testcases into the testbench. We will examine the waveform for each testcase and find out the possible sources of error if a certain testcase fails. We aim to test as many corner cases as possible. Finally, we will send out the report to design teams and repeat the process until the block is thoroughly tested and passes all the tests. We will also develop UVM testbenches to test other RTL blocks. With the use of UVM, verification of RTL blocks can be completed efficiently which can save us a lot of time and effort.