Power and dynamic noise considerations in high-performance CMOS VLSI

Dinesh Somasekhar, Purdue University

Abstract

With the continued scaling of CMOS VLSI, power dissipation of logic circuits has increasingly come to the forefront. Existing literature presents a variety of techniques for the minimization of power. Such methods have largely concentrated on medium and low performance circuit styles. Designers seeking higher performance have traditionally relied on circuits which are fast but hot. These circuits extract the maximum performance from a given CMOS technology by using designs which simplify synchronous clocking strategies, have low logic depths using high functionality gates, and have sized up gates to achieved the highest possible raw gate speed. This work addresses the problem of improving the power-performance product for such high performance gates. A new logic style differential current switch logic is proposed for implementing high functionality gates. A dominant style of high performance CMOS logic design, monotonic CMOS is evaluated. Traditional and new forms of monotonic CMOS styles are compared from a power, performance and dynamic noise margin viewpoint. Individual gate performance is not of interest when logic gates drive long global interconnects. Novel split gate circuits are shown to improve the performance of logic gates under such conditions. An implementation of methods for estimating the gate level dynamic noise margins under the influence of noise induced by signal coupling and constant supply rail bounce is presented. This implementation of the noise models is used to compare and contrast traditional and new monotonic CMOS logic styles.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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