Development of submicron CMOS in 6H-SiC

Man Pio Lam, Purdue University

Abstract

CMOS in 6H-silicon carbide (SiC) has been developed recently. Its major application is to be used as monolithic control circuits for SiC MOS-based power devices. From a system perspective, SiC CMOS is not well suited for high-end microprocessor design. However, in high-voltage power switching applications, CMOS circuits are required to provide rapid response time for the safety operation of a system. Despite previous developments in CMOS process technology which has enabled digital circuit operation using a 5 V power supply voltage, switching speeds are considerably slow. The main force to drive circuit speed is the shrinking of the minimum dimension of the transistor. As the feature sizes of MOS technologies are scaled to smaller dimensions, considerable challenges arise in the area of fabrication and device design. This work describes the recent progress in the development of 6H-SiC submicron CMOS. Conventional NMOS transistors fabricated with 0.5 micron (drawn) channel length have demonstrated acceptable short channel effects. PMOS transistors have experienced punchthrough with channel lengths below 0.8 Micron. Inverter and ring oscillators have been implemented with 0.8 Micron channel lengths. They can operate on a 2 V supply voltage and show a gate delay of 31 ns at VDD = 10 V. Considerable channel engineering has been performed on small PMOS transistors to obtain low leakage current. As the channel is scaled down further, the current drivability may not benefit accordingly. The influence of parasitic series resistance on the performance of scaled devices is examined.

Degree

Ph.D.

Advisors

Kornegay, Purdue University.

Subject Area

Electrical engineering|Electromagnetism|Materials science

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