Estimation of maximum power and delay for CMOS digital circuits

Chuan-Yu Wang, Purdue University

Abstract

Maximum instantaneous power dissipation in VLSI circuits has a great impact on circuit's long-term reliability and the design of power and ground lines. Excessive instantaneous power dissipation in VLSI circuits can lead to large IR drop degrading the signal levels and causing overheating, thereby reducing the chip's life-time and reliability. With today's critical demand on circuit's performance, it is imperative to have the accurate estimate of maximum power during the synthesis of highly reliable systems. Maximum power estimation for CMOS circuits is essentially a combinatorial optimization problem. It has the complexity exponentially proportional to the number of primary inputs (PI's). In the past, exhaustive simulation was used to obtain a lower bound of maximum power by directly searching for the optimal input patterns. However, the speed and performance of this traditional approach is not acceptable, especially for large-scaled circuits. Motivated by this, an Automatic Test Generation (ATG) based technique is developed to efficiently generate reliable estimates of the maximum power for large-scaled CMOS circuits. For a circuit described at gate-level, the ATG-based estimation assigns switchings to gates in an appropriate order and verifies the assignments based on a 9-Valued D algorithm (an ATG algorithm). In addition, a gradient-search based estimation for maximum power is presented, in which a continuous function denoting power can be efficiently formulated and maximized in the Euclidean space. Based on these techniques, the thesis considers efficiently estimating the maximum power for sequential/combinational circuits under various delay models. A pattern-dependent estimation of maximum power is proposed as a figure of merit for the ATG-based estimation, as well as the gradient-search based estimation. It can be utilized to evaluate the effectiveness of these two techniques from a statistical point of view. The thesis also addresses the problem of maximum power estimation considering uncertainties in gate delays. Hence, process variations can be easily considered during power estimation. Finally, we present a technique to accurately estimate critical path delays of a CMOS circuit considering capacitances internal to the logic gates.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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