Fabrication and characterization of dual-gate thin film SOI MOSFETs from silicon epitaxial lateral overgrowth

John Patrick Denton, Purdue University

Abstract

Silicon-on-Insulator (SOI) MOSFETs were uniquely fabricated using the epitaxial lateral overgrowth (ELO) of the selective epitaxial growth of silicon (SEG). The SOI material was fabricated using a "Recessed-well" technique. This technique consists of a silicon dioxide well in which ELO grown and the excess overgrowth was polished away. The resulting SOI island is planar to the field oxide and isolated from the bulk silicon substrate and from the seed window of the SEG. SOI MOSFETs were then fabricated in the SOI islands. SOI MOSFETs were designed and fabricated using a dual-gate structure. The backgates were fabricated using an isolated buried polysilicon gate structure or with a common substrate gate structure for comparison. The thickness of the SOI MOSFETs range from thick-film (0.25-0.65 microns) to thin-film (0.1-0.25 microns) in the channel region. SOI material fabricated from the Recessed-well method was 96% defect-free. The average density of interface traps (D$\rm\sb{it}$) for the backgate interface was measured to be 2.5 $\times$ 10$\sp{11}$ #/cm$\sp2$-eV for a polysilicon backgate and 1.55 $\times$ 10$\sp{11}$ #/cm$\sp2$-eV for a substrate backgate. Incorporation of the isolated polysilicon backgate and polysilicon gate oxide created no adverse effects in device performance as compared to the substrate gate devices with a normal thermal gate oxide. Both P-channel and N-channel dual-gate thin-film SOI MOSFETs were fabricated and examined. Electrical characterization showed excellent device operation. Backgate effective hole mobilities of 190 cm$\sp2$/v-sec, subthreshold leakages less then 1pA and inverse subthreshold slopes of 188mv/dec were measured for P-channel devices. These devices have several important applications in analog and low-power ULSI as the threshold voltage of each device can be individually and dynamically controlled by the isolated polysilicon backgate. Both N-channel and P-channel devices show a swing of 1 volt for the topgate threshold voltage for a swing of 2 volts on the backgate. The dynamic swing of the threshold voltage allows for current drive and device turn-on to be individually engineered for each device through its backgate. A new fabrication process to create SOI islands was developed and evaluated. Dual-gate thin-film SOI MOSFETs with each MOSFET having an isolated polysilicon buried gate were fabricated for the first time.

Degree

Ph.D.

Advisors

Neudeck, Purdue University.

Subject Area

Electrical engineering

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