Evaluation and application of epitaxial lateral overgrowth in silicon-on-insulator devices
Abstract
Epitaxial lateral overgrowth (ELO) is a versatile and unique technique for SOI device applications. Using ELO, silicon-on-insulator (SOI) devices can be fabricated along-side substrate devices on the same die. Multiple layers of SOI devices can be obtained for 3-dimensional integration as well. Exploiting these possibilities literally opens up new dimensions in IC processing. However, one disadvantage of ELO is that it is uneconomical to grow SOI islands that are much wider than 10$\mu$m. Further, for reliable ELO-SOI thickness control, a chemical mechanical polish (CMP) etch stop of local area field oxide or nitride is necessary around the device features. This implies that ELO-SOI CMOS circuits would not be able to achieve the packing density of other SOI CMOS. In this thesis, a large area ELO-SOI technique by double merged ELO (MELO) has been demonstrated which overcomes this crucial problem. The material quality of the MELO was studied by fabricating diodes on MELO SOI. It was demonstrated that once void free merge planes are obtained, the MELO material is of quality comparable to that of the substrate. Vertical seed ELO (VELO) is a new growth structure that is demonstrated in this thesis. The excellent quality of the VELO material has been shown, by studying diodes and MOSFETs fabricated in the VELO film. The ELO-SOI oxide interface formed by dry oxidation of the top SOI surface and the buried ELO-oxide interface showed comparable density of interface states. The SOI-oxide interfaces showed about 3 times greater density of interface states as compared to the substrate-oxide interface. This fact, which could be attributed to stresses in the 0.25 $\mu$m SOI film, however demonstrated that ELO growth over existing oxide results in nearly as good an interface quality as dry oxidation. Application of VELO in a novel high speed BJT structure and to a BiC-MOS cell have also been demonstrated. The VELO BJT has reduced collector-base capacitance to its intrinsic device value and involves a very simple fabrication procedure, which is a significant advancement to current state of the art devices. Although several VELO BJTs showed normal characteristics, the susceptibility of the structure to thermal stress induced emitter to collector pipes was documented. Thus, the applications and characterization of various new and unique ELO structures has been accomplished in this work.
Degree
Ph.D.
Advisors
Neudeck, Purdue University.
Subject Area
Electrical engineering
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