The development of a vertically integrated gallium arsenide bipolar/FET (BiFET) DRAM cell

Zicheng Ling, Purdue University

Abstract

A GaAs bipolar/FET (BiFET) dynamic RAM cell which provides non-destructive readout with internal gain is investigated. The cell consists of a bipolar transistor vertically integrated with a JFET readout transistor and a pn junction storage capacitor. Internal gain provided by the lateral JFET eliminates the requirement on minimum charge which must be stored for adequate signal-to-noise margin, and allows scaling the cell below the "million electron" limit of the conventional DRAM's. In this work, we designed and fabricated the first BiFET DRAM cell with an n-channel readout JFET. The operation of the memory cells was experimentally demonstrated, and cell storage time of about 20 seconds at room temperature was observed. The individual components of the BiFET cell were also characterized with particular attention to the leakage sources that limit the performance of the memory cell. We found that the reduced storage time is associated with npn junction capacitors, as compared to pnp capacitors. A study of storage capacitors indicates that the exposed n-type GaAs surface associated with npn junction storage capacitors exhibits large surface generation and leakage which severely limit the storage time of the capacitor. However, such large surface generation and leakage do not exist on p-type GaAs surfaces. Further study suggests that the dominant leakage mechanism along the n-type GaAs surface is surface mobile ion conduction. The leakage current, therefore, has a very long time constant, and is greatly affected by ambient. The source for the surface mobile ions is believed to be water vapor existing in the ambient. Finally, we fabricated and characterized a p-channel BiFET DRAM cell which eliminated the large exposed n-type surface associated with the storage capacitor. The complete read and write operation of the BiFET cell was demonstrated. The storage time of p-channel BiFET cells is about an order of magnitude longer than that of n-channel cells, and is comparable than the storage time of single capacitors on the same chip, indicating the addition of access BJT and readout JFET does not introduce extra leakage sources to the DRAM cell.

Degree

Ph.D.

Advisors

Copper, Purdue University.

Subject Area

Electrical engineering|Computer science

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