Executing MIMD programs on SIMD machines
Abstract
A massively parallel MIMD machine is costly and difficult to build. Implementations of MIMD machines seldom use more than 512 processors. On the other hand, a large scale SIMD machine is much easier and cheaper to build. Commercially available SIMD machines with more than several thousands of processors exist, e.g., the MasPar MP-1 and the Thinking Machine CM-2. By simulating MIMD programs on a SIMD architecture, we enable the SIMD machine to handle problems with irregular computational structures and synchronizations. This research examines some of the issues involved in the efficient simulation of MIMD programs on a SIMD machine. First, we discuss the simulation issues and present a model of scheduling MIMD instructions on a SIMD machine. Second, we outline and compare previous research efforts. Third, we present a framework for automatically constructing a code generator, assembler, and emulator for simulating MIMD/SPMD programs on SIMD machines. The flexible and expandable interpreter construction facilitates the implementation of different scheduling algorithms. Next, we describe the program execution model and analyze the program execution time of the interpreter with different instruction scheduling algorithms. Finally, we present the results of various scheduling heuristics on a stack machine model considering both simple and compound instructions. We give detailed simulation statistics and analyze them to illustrate the efficiency of various scheduling heuristics.
Degree
Ph.D.
Advisors
Quong, Purdue University.
Subject Area
Electrical engineering|Computer science
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