The design and development of a vertically integrated gallium arsenide bipolar dynamic memory
Abstract
This thesis documents the development of a gallium arsenide (GaAs) dynamic random access memory (DRAM) suitable for applications involving high temperatures or requiring short-term non-volatile storage. The process of developing this memory encompassed a broad range of topics including: the effect of e-beam metallization on the generation rate of bulk GaAs, the leakage associated with n-type GaAs surfaces, and the development of an invertable double heterojunction bipolar transistor for integration with a p-n-p storage capacitor to form a complete dynamic memory cell. E-beam metallization was found to adversely effect the storage times of the GaAs p-n-p capacitors. Consequently, a comprehensive study was undertaken to investigate the effect of e-beam metallization on the generation rate of bulk GaAs. This study included attempts to identify the deep level trap causing the increased generation as well as the mechanism responsible for the damage. Leakage along exposed mesa edges of the memory structure was also found to limit storage time. A selective-etch experiment was designed to compare the leakage along n- and p-type surfaces. This experiment revealed that leakage is several orders of magnitude greater on n-type surfaces. Moreover, capacitance transient and capacitance-voltage measurements were performed in an effort to identify the leakage mechanism. Finally, several integrated dynamic memory cells were investigated in order to identify a structure that would result in optimal performance in terms of access time, charge storage density, dynamic power dissipation, and storage time. A symmetrically doped, double heterojunction bipolar transistor (DHBT) was developed to address issues involving speed and power dissipation. The fabrication procedure involved proton implantation of a highly resistive buried layer into the extrinsic base region to provide transistors with comparable forward (emitter-up) and inverted (emitter-down) current gains. Room temperature storage times of the integrated cell including the DHBT access transistor were 30 sec as compared with 4.5 h for the optimal homojunction DRAM cell.
Degree
Ph.D.
Advisors
Melloch, Purdue University.
Subject Area
Electrical engineering
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