The design and analysis of superscalar architectures

James Kyle Pickett, Purdue University

Abstract

In the push for ever increasing performance out of processor architectures, there is a need to expand beyond the limitations of existing scalar approaches. Superscalar architectures provide one such means. By dynamically executing more than one instruction per clock cycle, superscalar architectures can improve performance without relying solely on technology improvements for these gains. This research examines various approaches to improving performance using superscalar design as well as examining the feasibility of implementing these approaches in current technology. Using the Verilog model developed, an analysis of in order and out of order issue, branch prediction, speculative loads, load latencies, number of functional units, and other parameters are achieved. The results indicate that a realizable approach with existing technology will yield a performance of three instructions per clock cycle on a continuous basis. Improvements in compiler technology in conjunction with the approach given in the thesis should yield an even greater enhancement in performance. This enhancement is from the false dependencies that are created in the compiled code for the scalar architecture that was used in this research.

Degree

Ph.D.

Advisors

Meyer, Purdue University.

Subject Area

Electrical engineering

COinS