Compiler-directed cache coherence for multiprocessors

Chiiwen Liou, Purdue University

Abstract

Although it is convenient to program large-scale multiprocessors as though all processors shared access to the same memory, it is very difficult to construct hardware directly implementing this model. Allowing each processor to have its own independent cache partially solves this problem, because it allows many memory references to be satisfied without accessing the shared main memory; however, it also introduces the possibility of having several different values cached with the same main memory address (one value per cache), and this could cause errors in program execution. Making the cache hardware always be coherent--one value per address--unfortunately also makes the hardware expensive and slow. The research presented here uses compiler analysis to generate explicit cache control instructions to ensure that all program memory accesses execute as though the caches were coherent. Compared to other approaches, the method given in this thesis is superior because the analysis more accurately models interactions between tasks.

Degree

Ph.D.

Advisors

Dietz, Purdue University.

Subject Area

Electrical engineering|Computer science

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