New approaches for VLSI layout compaction

Hung-Yi Tony Tu, Purdue University

Abstract

This dissertation focuses on the problem of layout compaction which arises during the design of VLSI circuits. From a given symbolic description of a layout, a layout compactor generates a layout having smaller area by re-positioning the layout cells. The re-positioning does not generally change the topology of the layout, and minimum and/or maximum distance requirements between the layout cells have to be satisfied. We present new and efficient algorithms for (1) generating a layout minimizing the total wire length, (2) generating a layout minimizing the longest wire length, and (3) generating a layout that minimizes a user-defined tradeoff function between the layout area and the wire length. Our algorithms have an $O(n\sb{h}\cdot n$logn) worst case running time, where n is the number cells and n$\sb{h}$ is the number of wires in the given layout. Compaction algorithms minimizing the layout area subject to constraints on wire length (or vice-versa) have previously been developed, but being able to trade layout area for wire length is novel in circuit compaction algorithms. The approach underlying out algorithm is that from a given initial layout, we generate a layout minimizing an objective by re-positioning certain cells. Determining which cells to re-position and by how much, is guided by computations on graphs modeling the topology of the layout and the minimum and maximum distance requirements between cells. For minimizing the total wire length, we partition the cells into groups, so that simultaneously shifting the cells in a group reduces the total wire length. In the algorithm minimizing the longest wire length, we assign a speed to every cell, so that moving cells with the assigned speeds decreases the length of all longest wires. To prove the termination and formulate the running times of the algorithms, interesting characterizations about optimum layouts are developed. We also consider how to perform compaction when the layout area contains forbidden regions. Forbidden regions can represent, for example, pre-positioned layout cells, wires or holes in the layout area. During compaction the positions of forbidden regions are fixed, and layout cells are allowed to slide over, but cannot overlap with forbidden regions. Thus, when compacting layout cells with forbidden regions, we do change the relative order between cells and forbidden regions. Compaction problems in which the relative order between cells is allowed to change are generally NP-hard. Nevertheless, in our situation when only the relative order between cells and forbidden regions is allowed to change, we develop a polynomial time algorithm for minimizing the layout area.

Degree

Ph.D.

Advisors

Hambrusch, Purdue University.

Subject Area

Computer science|Electrical engineering

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