Simulation-based performance evaluation of latency reduction and hiding mechanisms for uniprocessor and scalable multiprocessor systems

Silvio Picano, Purdue University

Abstract

Large latency memory access time is one of the fundamental problems precluding high performance processor utilization in scalable shared-memory multiprocessors. Scalable multiprocessors are those which exhibit higher performance levels when more hardware resources are added to the computer system. However, the addition of processing elements in a multiprocessor requires the addition of interconnection network capability and bandwidth to the memory subsystem to facilitate data sharing in parallel programs. Adding network capability in a scalable system, however, lengthens the average memory latency, which causes large amounts of idle time in current von Neumann processors. Several mechanisms to help reduce processor idle time due to shared memory accesses are the focus of this dissertation. A new mechanism based on dynamic scheduling and speculative execution is the primary latency hiding technique introduced here. By comparing several latency hiding and latency reduction techniques within a common set of system parameters, we can better judge the most cost effective mechanisms for future, large-scale, shared-memory multiprocessors. The simulation-based techniques developed provide the detailed and un-obtrusive statistics gathering capabilities necessary to perform these comparisons.

Degree

Ph.D.

Advisors

Meyer, Purdue University.

Subject Area

Electrical engineering

COinS