Evaluation of a double self-aligned silicon bipolar transistor utilizing selectively-grown single crystal extrinsic contacts

Jack Lavern Glenn, Purdue University

Abstract

Feasibility is demonstrated for a unique high speed double self-aligned bipolar junction transistor utilizing monocrystalline silicon base contacts. The transistor is designed for use in high-speed analog or digital applications where reduced parasitic capacitances and resistances are essential. The device design is unique in reducing extrinsic base/collector capacitance over single self-aligned bipolar transistors by using two relatively independent process techniques. First, base/collector capacitance is reduced by eliminating all misalignment tolerances between the outer edge of the collector and the base contact. Second, by using monocrystalline silicon instead of polycrystalline silicon base contacts, the contact area or "footprint" may be reduced without increasing contact resistance. Scaled-up versions of the high-speed transistor design were fabricated, electrically tested, and compared with computer simulations. Monocrystalline silicon extrinsic base contacts were fabricated using selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) in a reduced pressure chemical vapor deposition reactor using dichlorosilane and HCl in an H$\sb2$ carrier gas. Single self-aligned transistors (SSTs) with polycrystalline silicon contacted emitters were fabricated using monocrystalline silicon SEG base extrinsic contacts to examine the emitter/base junction. SSTs demonstrated maximum current gains of approximately 100, with nearly ideal junction behavior. Double self-aligned transistors (DSTs) were fabricated using both ELO and polycrystalline silicon extrinsic base contacts to examine the full device. DSTs yielded maximum current gains of between 100 and 160 with nearly ideal emitter/base junction behavior. Base/collector junctions, however, showed degraded ideality and increased leakage currents over the SSTs. The problem is believed to be related to the increased fabrication complexity required for the DSTs over the SSTs. Reverse biased junction capacitances for SSTs and DSTs were correlated to unit area values and demonstrated good agreement over different device sizes. Resistor test structures indicate that polycrystalline silicon extrinsic base contacts will have increased contact resistance over monocrystalline silicon base contacts by a factor of about 2. SUPREM-IV and PISCES-IIB two-dimensional computer simulations of the fabrication process and electrical characteristics respectively were compared against structural and electrical data to establish a base line for the simulation tools. Simulation tools were then used to predict the electrical behavior of the fully scaled-down version of the proposed device indicating a 45% decrease in base/collector capacitance over a comparable single self-aligned bipolar transistor. A simulation was also performed to measure the transient response of a 50mV applied input step to the base in a common emitter amplifier configuration. With a 5k$\Omega$ collector load, the proposed double self-aligned transistor exhibited a 20% faster collector current response time than a comparable single self-aligned device.

Degree

Ph.D.

Advisors

Neudeck, Purdue University.

Subject Area

Electrical engineering

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