Architecture and buffer management policies in fast packet switching
Abstract
This thesis includes two parts. In the first part, a new ATM switch architecture which employs multiple shared memory based switches as building modules is proposed. This architecture, called the Multiple Shared Memory (MSM) switch, has the best delay-throughput performance and permits global sharing of the total buffer space by all input/output ports. It also preserves packet sequencing and provides natural fault tolerance capability to module failures. One significance of this proposed switch is its substantial reduction of the buffer space. In the second part, a new buffer management policy called Drop on Demand is proposed. This policy improves the switch performance when compared with the existing ones under all traffic conditions. The key idea of this policy is that it dynamically allocates buffer space on the demand of each output port. With its simplicity, this policy may be easily implemented in a shared memory based switch. The optimal policy problem is also addressed and it is shown that the optimal buffer management policy can be obtained by solving a linear programming problem in a recursive fashion.
Degree
Ph.D.
Advisors
Hsiao, Purdue University.
Subject Area
Electrical engineering
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