Design and permutation routing algorithms of rearrangeable networks

Hasan Cam, Purdue University

Abstract

Balanced matrices are presented in the literature to identify the permutations realized by the shuffle-exchange network. In order to extend this work to the other interconnection networks and to facilitate the identification of permutations, this thesis introduces the concept of a frame and illustrations of different frames. The relationships between balanced matrices and frames are discussed in detail. Within the framework of balanced matrices, frames and graph theory, routing algorithms are developed to route permutations through some interconnection networks such as Benes, (2$n-$1)-stage shuffle-exchange, reverse baseline, a cascade of reverse baseline and ($n-$1)-stage shuffle-exchange, etc. The permutations realized by the subnetworks of these networks are identified and the properties of the permutations are analyzed. An interconnection network with N inputs and N outputs is said to be rearrangeable if it realizes every one of the N! permutations in a single pass. Benes network, which is a member of Clos' type networks, is a well known rearrangeable network. In this thesis, using balanced matrices, frames and graph theory, new proofs are provided for the rearrangeability of some networks such as Benes, three-stage Clos, reduced $\Omega\sb{N}\Omega\sbsp{N}{-1}$, etc. New rearrangeable networks whose topologies are very similar to Benes network are designed. A long-standing open question of whether the (2$n-$1)-stage shuffle-exchange network is rearrangeable is answered affirmatively. An important corollary of this result is the proof that two passes through Omega network are sufficient and necessary to implement any permutation. In addition to rearrangeability, fault-tolerance and the type of routing algorithm used in setting up the switches are the key issues in designing an interconnection network. In this thesis, four different self-routing rearrangeable networks, constructed from digit-controlled switches and concentrators, are presented. These networks use the destination tag routing scheme to realize any arbitrary permutation. One of these networks has O(log$\sbsp{2}{2}N$) gate-level delay with a very small constant and use O($N\sp2$log$\sb2N$) VLSI-level hardware. The propagation time of this network is less than that of any self-routing permutation network presented to date. Intrastage links, multiplexers and demultiplexers are added to this network to make it fault-tolerant.

Degree

Ph.D.

Advisors

Fortes, Purdue University.

Subject Area

Electrical engineering|Computer science

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