Compiler data layout and code transformation for reducing cache coherence overhead

Yeun-Jyr Ju, Purdue University

Abstract

This dissertation presents a systematic approach to reduction of cache coherence overhead in shared-memory multiprocessors. Rather than modifying the hardware coherence mechanism or using the compiler to insert directives which would aid the hardware, our approach is based on using the compiler to change the data access pattern of each program so that less coherence overhead will be incurred. Although changing the access pattern is an obvious technique, when the data layout for one array is changed to be optimal for a particular loop nest, other loop nests which access that array may be adversely affected. To find the optimal data layout for each array, the compiler must evaluate the coherence overhead for each loop nest which references that array. The choice of data layout is further complicated by the fact that loop nests also can be transformed so that different data layouts will perform better. The primary contribution of this thesis is a model for these interactions and a set of practical algorithms that allow globally near-optimal combinations of data layout and loop nest transformations to be found. To confirm the technique, a prototype implementation was constructed. The feasibility of the analysis was demonstrated by applying it to all 72 routines in the EISPACK library. In addition, four programs were analyzed, transformed, and then simulated in detail to determine the effectiveness in reducing cache coherence overhead. Execution time, bus traffic, cache coherence and cache miss overhead, etc., were all directly measured. Although the benefit of this approach is highly dependent on how carefully the program was originally written, three of the four benchmark programs showed greater than 25% reduction of bus traffic.

Degree

Ph.D.

Advisors

Dietz, Purdue University.

Subject Area

Electrical engineering

COinS