A catalytic migration approach for the design of windowing-oriented register file structures

Gihyun Jung, Purdue University

Abstract

This thesis is concerned with design and evaluation of register windowing structures. It gives an overview of catalytic migration methodology for processor design in conditions typical of GaAs technology (small chips and large ratio of off-chip to on-chip delays), and concentrates on its application to register file design. A multiple register windowing technique was recently employed by various systems which emphasize fast procedure (function) calls. However, it has several problems to overcome, such as the efficiency of using chip real estate, and heavy data traffic associated with context switching. To overcome these major problems, the windowing technique requires architectural support to minimize overhead encountered by frequent changes of procedures and tasks. As one way of providing this architectural support, a flexible window approach for the design of small register files is presented, analyzed, and compared with existing approaches in this thesis. It can alleviate the severe time consuming process for switching tasks and procedures, and utilize the chip real estate efficiently, retaining the advantages of multiple register window philosophy. The advantages and disadvantages of this new approach to register file design are discussed for both single task and multiple task cases, and the conditions under which it works better than existing approaches are outlined. Design tradeoffs are examined in both analytic and empirical studies. To verify the superiority, and get the optimal size of the flexible windowing scheme, it is simulated for a number of parameters using the ENDOT software package. The structures of the RISC II and the Flexible windowing scheme are constructed and simulated by ENDOT. To serve as a benchmark, a FIBONACCI program is modified to accept various number of local scalar variables, arguments passed, and a sufficient number of CALL/RETURN operations. To run the benchmark program, the instruction set for the U. C. Berkeley RISC II is used for both schemes. The results of simulations are summarized and analyzed in the conclusion of this thesis.

Degree

Ph.D.

Advisors

Meyer, Purdue University.

Subject Area

Electrical engineering

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