Barrier MIMD architecture: Design and compilation
Abstract
Barrier synchronization is an important mechanism for coordinating parallel processes. For this reason many efforts have been made to find efficient implementations in both hardware and software. In this thesis, several new designs for generalized barrier synchronization in hardware are introduced. It is shown that by adding an additional constraint to the definition of barrier synchronization, the static instruction scheduling properties of VLIW (Very Long Instruction Word) and SIMD (Single Instruction Stream, Multiple Data Stream) machines can be extended into the MIMD (Multiple Instruction Stream, Multiple Data Stream) domain. The result is that many conceptual synchronizations can be resolved at compile-time, without the use of a run-time synchronization mechanism. The proposed barrier mechanism extends the generality of efficient static scheduling to the parallel execution of loops, subroutine calls, and variable-time instructions. Machines that implement the new hardware barrier synchronization are called barrier MIMD architectures.
Degree
Ph.D.
Advisors
Dietz, Purdue University.
Subject Area
Electrical engineering|Computer science
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