Stochastic modeling and analysis of the propagation delays in logic circuits
Abstract
Aging and harsh environmental conditions can make logic gates change their internal delays, which has an impact on the time-domain characteristics of functional units in a typical processor. In other words, in some technologies, gates continue to function, but with different gate delays (e.g., GaAs). The propagation delay (after the effect of aging and harsh environmental conditions) of the functional unit is not known ahead of time. However, the probability distribution function (PDF) of the propagation delay (of a single gate) is typically known. Hence, the impact of the change in the time-domain characteristic of a functional unit can be studied with PDF of the propagation delay in the processor logic. A stochastic model and some mathematical tools have been developed in the past, to help in determining the PDF of an arbitrary combinational gate network. The research work presented in this thesis concentrates on extending the existing model and mathematical tools to sequential gate networks, CPU data paths, and systolic arrays. Since the straightforward application of the basic model and mathematical tools to CPU data path and systolic array may result in an untractable solution, an approach based on upper and lower bounds has been considered. Furthermore, an effort has been made to tighten these bounds. While this research is concerned with the PDF of propagation delay in a gate network, the model and mathematical tools can be generalized for computing PDF of other quantities in a network of processing-related units.
Degree
Ph.D.
Advisors
Milutinovic, Purdue University.
Subject Area
Electrical engineering
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