An architecture for high-speed packet-switched networks

Rajendra Shivaram Yavatkar, Purdue University

Abstract

The emergence of performance intensive distributed applications is making new demands on computer networks. Distributed applications access computing resources and information available at multiple computers located across a network. Realizing such distributed applications over geographically distant areas requires access to predictable and high performance communication. Circuit switching and packet switching are two possible techniques for providing high performance communication. Circuit switched networks preallocate resources to individual sources of traffic before any traffic is sent, whereas packet switched networks allocate resources dynamically as the traffic travels through the network. The advantage of circuit switching lies in guaranteed performance due to reserved capacity, but the network capacity is wasted when circuits are idle. Packet switched networks have been preferred in data networks due to their lower cost and efficient utilization of network resources. However, the major limitation of current packet switched networks lies in their inability to provide predictable performance. This dissertation proposes a new architecture for providing predictable high performance in high speed packet switched networks. The architecture combines the advantages of circuit switching and packet switching by providing two services: datagrams and flows. The datagram service supports best-effort delivery of traffic. The main liability of a datagram service lies in congestion. To avoid congestion, the architecture uses a novel, rate-based congestion control scheme. To support applications that demand specific performance guarantees, the architecture provides an abstraction called a flow. A flow is a communication channel that has specific performance characteristics associated with its traffic. When requesting a flow, a source specifies the performance needs and a destination. The underlying delivery system guarantees to meet those needs by pre-allocating resources along a selected path to the destination. An experimental evaluation using a prototype network demonstrates the viability of the architecture in providing predictable, high performance. The importance of this research extends beyond providing another architecture for packet switched networks. The successful implementation of the flow abstraction demonstrates the feasibility of providing predictable performance in packet switched networks. Supporting both datagrams and flows in the same network adds flexibility to packet switched networks to accommodate applications that span a wide range of performance requirements. Regulating rates at which data enters a packet switched network to prevent congestion provides a new direction for exploring ways of controlling datagram congestion.

Degree

Ph.D.

Advisors

Comer, Purdue University.

Subject Area

Computer science

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