Parallel algorithms and VLSI architectures for robotics and assembly scheduling

Po-Rong Chang, Purdue University

Abstract

This research addresses two intensive computational problems of designing VLSI architectures for robotic computations and of implementing the assembly scheduling problem on a highly parallel artificial neural network. In designing VLSI architectures for a complex computational robotic task, the functional decomposition of the task into a set of computational modules can be represented as an acyclic data flow graph (ADFG) which can be mapped into the VLSI architecture by an existing systolization procedure. An efficient graph decomposition technique has been developed which utilizes the critical path concept to decompose a large-scale directed ADFG into a set of connected subgraphs, and the integer linear optimization technique can be used to solve the buffer assignment problem in each subgraph in pseudo-polynomial time. The other equally important computational problem is the NP -complete assembly scheduling problem which is difficult to be solved by traditional machines. The real-time assembly scheduling problem is characterized by a bipartite graph model and re-formulated as a two-stage optimization: the linear assignment problem for the optimal arrangement of part-feeding components in the assembly system and the constrained traveling salesman problem (TSP) for the final ordering problem. To solve this assembly scheduling problem effectively, massively parallel network systems based on neural network models are exploited to achieve the real-time computational requirement. A computer simulation of an assembly scheduling problem of size 20 was conducted to verify the performance of the neural network implementation.

Degree

Ph.D.

Advisors

Lee, Purdue University.

Subject Area

Electrical engineering

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