Systematic design of computational arrays

Mokhtar A Aboelaze, Purdue University

Abstract

In this thesis we discuss some aspects of the design of a system of systolic arrays, from the VLSI layout level to the system level. First, we discuss 3-D VLSI layout, where tighter lower and upper bounds for the volume and maximum wire length for the layout of the different families of graphs in a 3-D environment were developed. Except in two cases, all the bounds for the volume are optimal. The first case is the one-active-layer layout of the planar graphs, the other is the unrestricted layout for graphs with separators N$\sp{\rm q}$, q = 2/3. A cost model for reflecting the real cost of the layout, instead of taking the volume as a measure of cost, was also developed. In Chapter 3, we develop a methodology for designing a systolic array starting from recurrence equations. The idea of Control Flow Systolic Arrays to handle uniform, as well as nonuniform recurrence equations, is developed. This methodology is basically a search for a heuristic solution in the space of all the possible solutions. Because of the unlimited search space, the search process must be guided for the search to be completed in a reasonable amount of time. Chapter 4 introduces the idea of converting the data between two systolic arrays that were directly interfaced, instead of using a common memory which would be a bottleneck for the whole system. The minimum number of buffers required to convert the data between two given distributions was also calculated, a general purpose converter was also proposed.

Degree

Ph.D.

Advisors

Wah, Purdue University.

Subject Area

Electrical engineering

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