MULTIPROCESSOR DESIGN TRADEOFFS IN WSI

IN-GYU PARK, Purdue University

Abstract

Rather than partitioning a Silicon/GaAs wafer into VLSI individual chips as usually separately manufactured, tested and then assembled, an entire system is assembled on a single wafer by connecting individual chips together using on-wafer wiring. Ultimately, a single system will fill the entire wafer. In this case, a wafer may be termed wafer-scale integrated (WSI) system. Therefore, this allows a powerful multiprocessor system to be implemented on a single wafer. A critical factor behind the success of the multiprocessor system is the careful optimization which will be performed during its design. On any given wafer, many of the modules will contain defects. Defects are randomly distributed over the wafer surface. Therefore, we first develop a process model of wafer. The analysis is based on the properties of the defect density function and the module size. Next, we are interested in wafer scale implementation of architectures to achieve the fault tolerant multiprocessor systems. Finally, we discuss various interconnection issues for WSI, either presently available or projected into the future. The key challenge in WSI is the development of suitable linking technologies for implementing restructurability of interconnection. It is hoped that this work will bring out the significance of evaluating the design tradeoffs over the whole spectrum, ranging from the selection of a system architecture down to the choice of the interconnection circuitry between processors.

Degree

Ph.D.

Subject Area

Electrical engineering

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