COMPUTATION OF DELAYS FOR TIMING VERIFICATION (PIECEWISE LINEAR, SENSITIVITY)

YASSIN SAAD ELCHERIF, Purdue University

Abstract

Timing of digital integrated circuits is influenced by variations of the signal propagation delay. Delay variations are due to several factors including: (1) Variations in wafer processing. (2) Changes in signal routing made after the initial design. (3) Changes in the temperature of the operating environment. A circuit designer is expected to account for all such variations while verifying the circuit timing. Timing verification is handled by one of the following ways: (1) Nonlinear transient circuit analysis using physical device models, which is the most accurate option and the most expensive as well. (2) Timing analysis by approximate models, for example by using linear RC models and ignoring bootstrapping capacitors in MOS circuits. (3) Logic simulation. (4) Mixed mode simulation where the main environment is that of logic simulation. (5) Path delay analysis. Options (3) to (5) require the availability of precise delays of logic components and routing wires and the range of variation of these delays. Techniques for timing verification are based on either the worst case delays or the delay variance. We will focus on computing component output delays and their variations which are caused by variations in device model parameters. Our techniques are suited for bipolar technology which receives little attention compared to the multitude of methods proposed for MOS. Most of these methods cannot be used for bipolar circuits because of the inability to handle nonlinear capacitors of bipolar junctions. We use piecewise linear (PWL) models of the i-v characteristics of junction diodes, while maintaining capacitors in their nonlinear form. A hybrid multiport formulation of the circuit equations allows capacitors to appear explicitly which makes it possible to use this combined nonlinear-PWL model. The solution of the network equations is obtained by a complementary pivot algorithm. The iterative algorithm needs to be applied only at those instants when a breakpoint is encountered in the PWL characteristics. The time delays are defined formally in a way which is consistent with three-state logic simulation. For computing the required delay variation, we derive a method for computing the delay sensitivity with respect to the model parameters, using the adjoint network approach. This approach is extended to handle the PWL models. The solution of the adjoint equations follows directly from the original network solution. The availability of the sensitivity information enables the computation of the delay variance by the efficient use of Monte Carlo method.

Degree

Ph.D.

Subject Area

Electrical engineering

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