MULTISTAGE INTERCONNECTION NETWORKS: MODELING, PERFORMANCE ANALYSIS, DESIGN, AND FAULT LOCATION (COMPUTER ARCHITECTURE, PARALLEL PROCESSING)
Abstract
Traditional computer system design costs have been dominated by development and production costs of the hardware. With the advent of very large scale integrated circuit technology, relatively inexpensive hardware systems and subsystems are becoming readily available. The modern computer system architect can now design, build, and then validate new design concepts that would have been at best "paper designs" only a few years ago. The result has been the greater use of multiple-processor system designs that employ processors operating in parallel to achieve high levels of computational power. This thesis is a report of research into the design and the performance analysis of multistage interconnection networks for use in parallel processing "supersystems." In particular, the topics of investigation include: the modeling and performance analysis of circuit and packet switched networks, the effects of partitioning on network operation and performance, the effects of multiple-packet message formats, the performance differential between circuit and packet switched networks, the techniques necessary for locating faults in networks that employ distributed control schemes, and the design and implementation of a network that is suitable for inclusion in the PASM parallel processing system prototype.
Degree
Ph.D.
Subject Area
Electrical engineering
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