A FAULT-TOLERANT INTERCONNECTION NETWORK AND IMAGE PROCESSING APPLICATIONS FOR THE PASM PARALLEL PROCESSING SYSTEM
Abstract
The demand for very high speed data processing coupled with falling hardware costs has made large-scale parallel and distributed computer systems both desirable and feasible. Two modes of parallel processing are single instruction stream--multiple data stream (SIMD) and multiple instruction stream--multiple data stream (MIMD). PASM, a partitionable SIMD/MIMD system, is a reconfigurable multimicroprocessor system being designed for image processing and pattern recognition. An important component of these systems is the interconnection network, the mechanism for communication among the computation nodes and memories. Assuring high reliability for such complex systems is a significant task. Thus, a crucial practical aspect of an interconnection network is fault tolerance. In answer to this need, the Extra Stage Cube (ESC), a fault-tolerant, multistage cube-type interconnection network, is defined. The fault tolerance of the ESC is explored for both single and multiple faults, routing tags are defined, and consideration is given to permuting data and partitioning the ESC in the presence of faults. The ESC is compared with other fault-tolerant multistage networks. Finally, reliability of the ESC and an enhanced version of it are investigated. A knowledge of the performance of various switching element designs is important to the engineering of interconnection networks. Typically, networks proposed for parallel systems have been designed with two-input/two-output switches. VLSI technology allows implementation of complex circuits as a single device. The performance of four-input/four-output switches under various message loading conditions is analyzed and their use in the ESC considered. Finally, a parallel digital image processing scenario for implementation on a computer system such as PASM is analyzed. Contour extraction is chosen as the focus because it is a key step in many applications and presents a multifaceted challenge to a parallel computer. Issues studied include parallel formulation of the constituent algorithms, mapping the algorithms and sizing the machine, quality of results, and implications for network design and system architecture.
Degree
Ph.D.
Subject Area
Electrical engineering
Off-Campus Purdue Users:
To access this dissertation, please log in to our
proxy server.