PIPELINING AND DATAFLOW TECHNIQUES FOR DESIGNING SUPERCOMPUTERS

SHUN-PIAO SU, Purdue University

Abstract

Extensive research has been conducted over the last two decades in developing supercomputers to meet the demand of high computational performance. This thesis investigates some pipelining and dataflow techniques for designing supercomputers. In the pipelining area, new techniques are developed for scheduling vector instructions in a multi-pipeline supercomputer and for constructing VLSI matrix arithmetic pipelines for large-scale matrix computations. In the dataflow area, a new approach is proposed to dispatch high-level functions for dependence-driven computations. A parallel task scheduling model is proposed for multi-pipeline vector supercomputers. This model can be applied to explore maximal concurrencies in vector supercomputers with a structure generalized from the CRAY-1, CYBER-205, and TI-ASC. The optimization problem of simultaneously scheduling multiple pipelines is proved to be NP-complete. Thus, heuristic scheduling algorithms for some restricted classes of vector task systems are developed. Nearly optimal performance can be achieved with the proposed parallel pipeline scheduling method. Simulation results on randomly generated task systems are presented to verify the analytical performance bounds. For dependence-driven computations, a dataflow controller is used to perform run-time scheduling of compound functions. The scheduling problem is shown to be NP-complete. Several heuristic scheduling strategies are proposed based on the time and resource demands of compound functions. A series of simulation experiments is carried out to compare the relative performances of various scheduling strategies. It is found that the Most Resource First strategy is superior to others. A class of pipelined matrix arithmetic networks is proposed based on Hwang-Cheng's matrix partitioning algorithms. Only a few types of VLSI modules are needed to synthesize the networks. These networks are pipelined with high system throughput. Application of these pipelines to pattern recognition has been investigated. Performance of the proposed hardware pattern recognizer is shown to be superior to that of the conventional software approach using a uniprocessor computer. The results obtained in this thesis should be useful to system designers and performance evaluators of supercomputers.

Degree

Ph.D.

Subject Area

Computer science

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