PARALLEL PROCESSNG AND VLSI ARCHITECTURES FOR SYNTACTIC PATTERN RECOGNITION AND IMAGE ANALYSIS (MIMD, SIMD)
Abstract
Computation speed of syntactic pattern recognition and image analysis algorithms have always been regarded as slow. We propose several parallel processing techniques, especially for the syntactic analyzer, to speed up the computation. The distance calculations between strings and trees have been implemented on three different parallel processing systems, namely, the SIMD system, the dedicated SIMD system and the MIMD system. The results show that distance calculation can be sped up when it is implemented on a parallel computer. Earley's algorithm has a wide applications in many fields. We propose a parallel Earley's algorithm, and implement the recognition algorithm on a VLSI architecture, the parse extraction algorithm and the complete algorithm on a processor array. This parallel execution only takes linear time. Simulation results prove the correctness of this design. The same Earley's algorithm has been extended to process erroneous input data. This error-correcting syntactic recognizer has also been implemented on a VLSI system. The results from the simulation not only prove the correctness of this design, but also indicate that this recognizer can be used to classify patterns.
Degree
Ph.D.
Subject Area
Computer science
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