SCHEDULING PARALLEL PROCESSORS WITH DUE DATES AND SETUP
Abstract
Parallel processor scheduling to minimize maximum tardiness with uniform processors is investigated. Jobs belong to classes; setup between jobs of different classes is required. The objective of the research is to develop and evaluate a heuristic scheduling procedure, since optimization is computationally intractable. The problem was divided into an allocation and a sequencing stage. The allocation phase attempts to balance makespan and due dates. The sequencing stage uses job reordering operations to reduce maximum tardiness. Bounds on maximum tardiness are developed and a theorem is introduced which significantly reduces the number of sequences which must be explicitly considered. The sequencing alone and the combined parallel processor scheduling procedure are tested by comparison with th optimal solutions for a large group of problems. Results indicate that both procedures, though heuristic in nature, provide good solutions with little expenditure of computational resources, and thus are viable for large problems.
Degree
Ph.D.
Subject Area
Industrial engineering
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