VLSI placement algorithms for better detailed routability

Shuai Li, Purdue University

Abstract

The placement step in VLSI physical design flow deals with the problem of determining the locations of circuit elements, which are typically represented as rectangles of various sizes, with the goal of easing the difficulty of the next step in the flow, namely, routing, which realizes the physical connections between these circuit elements. Consequently, the placement step has a direct effect on the total wirelength of the realized connections of a circuit and perhaps more important, the feasibility of realizing these connections, or the routability of the placement solution. This thesis focuses on developing placement algorithms for generating placement solutions with shorter routed wirelength and better routability. Instead of using only an intermediate global routing solution for evaluation, we always assess the quality of a placement solution with a detailed routing solution in terms of the total routed wirelength and the total number of routing violations. The placement step is conventionally performed in two phases: global placement followed by detailed placement. We propose an analytical global placer for routability-driven placement of fixed-size circuits. By applying a new mathematical formulation, the global placer manages to alleviate pin congestion when distributing cells. Moreover, we adopt a scaled smoothing method to reduce the negative influence of macro blocks. On average, detailed routing solutions with smaller wirelength and fewer design rule violations can be achieved on placement results generated with the proposed global placer. For detailed placement, we focus on sliding window techniques, which rearrange cells in local windows and do not perturb routability much. Specifically, we develop a Mixed Integer Programming (MIP) model that allows the detailed placement of windows containing more cells to be optimized more efficiently. In particular, by ignoring some integer variables in the model, the solution time for the optimization of windows from large-scale mixed-size circuits can be shortened greatly. With the application of our detailed placer on the placement results of other detailed placement techniques, routed wirelength can be reduced while similar level of detailed-routability is retained for most circuits.

Degree

Ph.D.

Advisors

Koh, Purdue University.

Subject Area

Computer Engineering|Electrical engineering

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